The invention relates to conflict checking in a multiprocessor system with speculative execution.
A multiprocessor system typically includes cache memory. In the context of speculative execution, cache memory will normally include various data versions, i.e. versions that are created or read by threads of a program executing in parallel. These versions may be in conflict with one another. In other words, as threads execute out of order they may create or access data that is visible for only a subset of threads.
In the case of the type of speculation called TM: when a thread reads data speculatively from a line, it sets its speculative reader bit in its local cache and the line is starting at that point in a “speculatively read, shared” state. If any thread now tries to write to the line, no matter to which point within the line, this write is broadcast to all caches. The standard coherence scheme without speculation would in this case invalidate all copies in all caches except for the local cache of the writer, and would mark the local version of the writer as modified. In TM, the transition from “speculatively read, shared” to invalid would cause the transaction for this core to fail and to be invalidated.
In the case of the type of speculation known as TLS, the most simple implementation behaves like TM described above. More evolved schemes compare the speculation IDs of the writer with the one used by the core that has the line in “speculatively read, shared” state. If the reader thread is older than the writer the reader is not invalidated and the line is not invalidated from its cache as well.